View DAC1353X_4751253.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

functional block diagram general description the DAC1353X is a cmos 8-bit d/a converter for general applications. this digital to analog converter has a r-string structure. the maximum conversion rate of DAC1353X is 2msps and supply voltage is 1.2v single. typical applications hard disk drive (hdd) battery operated instruments motor control systems general applications features resolution : 8bit differential linearity error : 1.0 lsb integral linearity error : 1.0 lsb maximum conversion rate : 2msps low power consumption : 3.6mw power down mode operation temperature range : 0o c ~ 70o c power supply : 1.2v single 1.2v 8bit 2msps dac DAC1353X samsung electronics co. ltd ver 1.0 (mar. 2002) this datasheet is a preliminary version. no responsibility is assumed by sec for its use nor for any infringements of patents or other rights of third parties that may result from its use. the content of this datasheet is subject to change without any notice. d[7:0] 8 n r-string vrb vrt vout pwdnb avdd12a avss12a avdd12d avss12a dout 1-of-2 n decoder dout 1-of-2 m decoder m avbb 2 n 2 m pwdnb op amp _ + slot cell bias gen. pwdnb nbias d[7:0] 8 n r-string vrb vrt vout pwdnb avdd12a avss12a avdd12d avss12a dout 1-of-2 n decoder dout 1-of-2 n decoder dout 1-of-2 m decoder dout 1-of-2 m decoder m avbb 2 n 2 m pwdnb op amp _ + slot cell bias gen. pwdnb nbias
sec asic DAC1353X 1.2v 8bit 2msps dac analog core pin description core configuration i/o type abbr. ai : analog input di : digital input ao : analog output do : digital output ab : analog bidirectional db : digital bidirectional ap : analog power dp : digital power ag : analog ground dg : digital ground 2/12 name i/o type i/o pad pin description d[7:0] di picc_abb digital input data (8bit) d[7] : msb , d[0] : lsb pwdnb di picc_abb power down (active low) vrt ab pia_abb voltage reference top vrb ab pia_abb voltage reference bottom nbias ab pia_abb bias generator output voltage vout ao poa_abb analog voltage output avdd12a ap vdd12t_abb analog power (+1.2v) avss12a ag vsst_abb analog ground (0.0v) avdd12d dp vdd12t_abb digital power (+1.2v) avss12d dg vsst_abb digital ground (0.0v) avbb ag vbb_abb analog sub bias (0.0v) vrt vrb d[7:0] vout avdd12a avss12a avdd12d avss12d avbb DAC1353X pwdnb vrt vrb d[7:0] vout avdd12a avss12a avdd12d avss12d avbb DAC1353X pwdnb
sec asic DAC1353X 1.2v 8bit 2msps dac analog absolute maximum ratings characteristics symbol value unit supply voltage vdd (avdd12a,avdd12d) 1.2 v analog output voltage vout 0.05 to 1.15 v digital input voltage d[7:0] vss to vdd v reference voltage vrt vrb 1.15 0.05 v operating temperature range topr 0to70 c notes : 1. absolute maximum rating specifies the values beyond which the device may be damaged permanently. exposure to absolute maximum rating conditions for extended periods may affect reliability. each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. all voltages are measured with respect to vss(avss12a or avss12d or avbb) unless otherwise specified. 3. 100pf capacitor is discharged through a 1.5k ? resistor (human body model) recommended operating conditions characteristics symbol min typ max unit supply voltage avdd12a - avss12a avdd12d - avss12d 1.08 1.2 1.32 v supply voltage difference avdd12a - avdd12d -0.1 0.0 0.1 v reference voltage vrt vrb - 0.05 - - 1.15 - v digital input 'low' voltage digital input 'high' voltage vil vih - 0.7 vdd - - 0.3 vdd - v operating temperature topr 0 - 70 c note : it is strongly recommended that to avoid power latch-up all the supply pins(avdd12a,avdd12d) be driven from the same source. 3/12
sec asic DAC1353X 1.2v 8bit 2msps dac analog dc electrical characteristics (converter specifications : avdd12a=avdd12d=1.2v, avss12a=avss12d=avbb=0v, pwdnb=high, top=25 c, vrt=1.2v, vrb=0.0v unless otherwise specified.) characteristics symbol min typ max unit conditions resolution bit - - 8 bits - differential linearity error dle - 1.0 - lsb - integral linearity error ile - 1.0 - lsb - zero scale error 1 v zse - 10 - mv vrt=1.15v , vrb=0.05v full scale voltage error 2 v fse - 10 - mv maximum output voltage vo max - 1.146 - v vo max = vout(d[7:0]=high) v lsb =vo max / 255 lsb size v lsb - 4.49 - mv note 1 : v zse =vout(d[7:0]=low) - vrb 2:v fse =vout(d[7:0]=high) - {(vrt-vrb) 255/256 + vrb} ac electrical characteristics (converter specifications : avdd12a=avdd12d=1.2v, avss12a=avss12d=avbb=0v, load cap=20pf, resistive load=100k top=25c, vrt=1.2v, vrb=0.0v unless otherwise specified.) characteristics symbol min typ max unit conditions maximum conversion rate f c - - 2 msps data rate = 2mhz dynamic supply current ivdd1 - 3 - ma ivdd1 = i avdd12a +i vrt +i avdd12d data rate = 2mhz dynamic supply current (power down mode) ivdd2 - - 10 ua ivdd2 = i avdd12a +i avdd12d data rate = 2mhz pwdnb=low analog output delay td - 120 - ns data rate = 2mhz data : all low all high analog output rise time tr - 90 - ns data rate = 2mhz data : all low all high analog output fall time tf - 130 - ns data rate = 2mhz data : all high all low analog output settling time ts - 430 - ns data rate = 2mhz data : all low all high vrt = vdd/2 powerdownontime ton - 60 - ns pwdnb : high low power down off time toff - 900 - ns pwdnb : low high 4/12
sec asic DAC1353X 1.2v 8bit 2msps dac analog timing diagram 1. output delay measured from the 50% point of the rising edge of input data to the full scale transition. 2. settling time measured from the 50% point of full scale transition to the output remaining within 1/2 lsb. 3. output rise/fall time measured between the 10% and 90% points of full scale transition. functional description 1. the DAC1353X has a r-string block for 10bit and an opamp block for driving output. 2. the digital outputs of two decoders decide the voltage level of r-string block. 3. output of the r-string block is driven by opamp. 4. bias gen. consists of simple current source to provide constant current independent of supply voltage and temperature. 5. in power down mode, only analog current(i avdd12a ) is reduced. data vout td 00000000 11111111 50% 50% vout 00000000 11111111 00000000 10% 90% data tr tf vout 00000000 11111111 00000000 50% 0.5lsb data ts pwdnb vout ton 50% toff 50% 0.5lsb 0.5lsb 0.0v 5/12 v vrt vrb 2 (*dn)+vrb rstring 8 n n0 7 2 = ? =
sec asic DAC1353X 1.2v 8bit 2msps dac analog core evaluation guide testability whether you use mux or the internal logic for testability, it is required to be able to select the values of digital inputs ( d[7:0] ). see above figure. only if it is, you can check the main function. ( linearity ) normal test condition : vrt=1.15v , vrb=0.05v , pwdnb=high location description ct 10uf tantalum capacitor cc 0.1uf ceramic capacitor 6/12 host dsp core mux test path 8 8 8 cc ct avdd12d avss12d avdd12a avss12a avbb 1.2v gnd 1.2v gnd cc ct ct cc ct cc 1.2v gnd 0.0v gnd d[7:0] pwdnb vrt vrb vout DAC1353X vout host dsp core mux test path 8 8 8 cc ct avdd12d avss12d avdd12a avss12a avbb 1.2v gnd 1.2v gnd cc ct ct cc ct cc 1.2v gnd 0.0v gnd d[7:0] pwdnb vrt vrb vout DAC1353X vout
sec asic DAC1353X 1.2v 8bit 2msps dac analog core layout guide pin name property pin usage pin layout guide d[7:0] di internal / external 1. digital input signal lines must have same length to reduce propagation delay. pwdnb di internal / external vrt ab external 1. voltage reference lines (vrt and vrb) must be wide metal to reduce voltage drop of metal lines. 2. vout signal should not be crossed by any signals and should not run next to digital signals to minimize capacitive coupling between the two signals. vrb ab external nbias ab internal / external vout ao internal / external avdd12a ap external 1. it is recommended that you use thick analog power metal. when connected to pad, the path should be kept as short as possible. 2. digital power and analog power are separately used. 3. each analog power / ground (avdd12a, avss12a and avbb) pin have two ports and you may connect just one of them, because they are connected internally. avss12a ag external avdd12d dp external avss12d dg external avbb ag external 1. when the core block is connected to other blocks, it must be double guard-ring using n-well and p+ active to remove the substrate and coupling noise. in that case, the power metal should be connected to pad directly. 2. the bulk power is used to reduce the influence of substrate noise. 7/12 r-string amp decoders p+ guardring nwell guardring vout pwdnb vrb d[7:0] avdd12a avss12a avbb avdd12d avss12d vrt avdd12a avss12a avbb nbias bias gen. r-string amp decoders p+ guardring nwell guardring vout pwdnb vrb d[7:0] avdd12a avss12a avbb avdd12d avss12d vrt avdd12a avss12a avbb nbias bias gen.
sec asic DAC1353X 1.2v 8bit 2msps dac analog layout guide with pads (1) it is recommended that you use thick analog power metal. when connecting to pad, the path should be kept as short as possible, and use branch metal to connect to the center of analog switch block. (ex. if analog supply current is 30ma, then analog power metal width should be kept over than 30um) (2) digital power and analog power should be used separately. (3) the analog core should be placed near pad as close as possible . (4) bulk power is used to reduce the influence of substrate noise. (5) vout signal should not be crossed by any signals and should not run next to digital signals to minimize capacitive coupling between the two signals. (6) if you want to control the analog current, nbias pin should be connected to i/o pad. 8/12 DAC1353X pwdnb vrb d[7:0] avdd12a avss12a avbb avdd12d avss12d vrt nbias avdd12a avss12a avbb vout met1 met2 met3 (option) avdd12d avss12d (nbias) avdd12a avss12a avbb vout vrt vrb (digital domain) (analog domain) DAC1353X pwdnb vrb d[7:0] avdd12a avss12a avbb avdd12d avss12d vrt nbias avdd12a avss12a avbb vout met1 met2 met3 (option) avdd12d avss12d (nbias) avdd12a avss12a avbb vout vrt vrb (digital domain) (analog domain)
sec asic DAC1353X 1.2v 8bit 2msps dac analog package configuration location description ct 10uf tantalum capacitor cc 0.1uf ceramic capacitor l1~l3 ferrite bead ( 0.1mh ) 9/12 vrb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] vrb avdd12d avss12d avbb avss12a avss12a avdd12a avdd12a vout vrt + ct cc pwdn vout vrt (1.15v typ.) (1.2v in normal operation) ct + cc (0.05v typ.) DAC1353X nc nc nc nc nc nc nc nbias nc nc pwdnb nc nc nc nc nc nc d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] nc nc nc nc nc nc nc nc nc nc nc nc nc cc ct + 0.0v 1.2v (vss) (vdd) l1 l2 + ct cc vrb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] vrb avdd12d avss12d avbb avss12a avss12a avdd12a avdd12a vout vrt + ct cc pwdn vout vrt (1.15v typ.) (1.2v in normal operation) ct + cc (0.05v typ.) DAC1353X nc nc nc nc nc nc nc nbias nc nc pwdnb nc nc nc nc nc nc d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] nc nc nc nc nc nc nc nc nc nc nc nc nc cc ct + 0.0v 1.2v (vss) (vdd) l1 l2 + ct cc
sec asic DAC1353X 1.2v 8bit 2msps dac analog package pin description name pin no i/o type pin description avdd12d 1,2 dp digital power (1.8v) avss12d 3,4 dg digital ground (0.0v) d[7:0] 10~17 di digital input data vrb 23,24 ab voltage reference bottom (0.0v) vrt 25,26 ab voltage reference top (1.8v) vout 29,30 ao analog voltage output pwdnb 31 di power down mode (low active) avdd12a 36,37 ap analog power (1.8v) avss12a 38,39 ag analog ground (0.0v) nbias 45 ab bias generator output voltage avbb 47,48 ag analog sub bias (0.0v) nc 5,6,7,8,9,18,19 20,21,22,27,28, 32,33,34,35,40, 41,42,f43,44,46 ao no connection i/o type abbr. ai : analog input di : digital input ao : analog output do : digital output ab : analog bidirectional db : digital bidirectional ap : analog power dp : digital power ag : analog ground dg : digital ground 10 / 12
sec asic DAC1353X 1.2v 8bit 2msps dac analog pc board layout consideration 1. pc board considerations to minimize noise on the power lines and the ground lines, the digital inputs need to be shielded and decoupled. this trace length between groups of vdd (avdd12a, avdd12d) and vss (avss12a, avss12d) pins should be as short as possible so as to minimize inductive ringing. 2. supply decoupling and planes for the decoupling capacitor between the power line and the ground line, 0.1uf ceramic capacitor is used in parallel with a 10uf tantalum capacitor. the digital power plane(avdd12d) and analog power plane(avdd12a) are connected through a ferrite bead, and also the digital ground plane(avss12d) and the analog ground plane(avss12a). this ferrite bead should be located within 3inches of the DAC1353X. the analog power plane supplies power to the DAC1353X of the analog output pin and related devices. 11 / 12
sec asic DAC1353X 1.2v 8bit 2msps dac analog feedback request we appreciate your interest in out products. if you have further questions, please specify in the attached form. thank you very much. dc / ac electrical characteristic characteristics min typ max unit remarks supply voltage v power dissipation mw resolution bits analog output voltage v operating temperature c output load capacitor pf output load resistor k ? integral non-linearity error lsb differential non-linearity error lsb maximum conversion rate mhz voltage output dac reference voltage top bottom v analog output voltage range v digital input format binary code or 2's complement code current output dac analog output maximum current ma analog output maximum signal frequency khz reference voltage v external resistor for current setting(rset) w pipeline delay sec - do you want to power down mode? - do you want to internal reference voltage(bgr)? - which do you want to serial input type or parallel input type? - do you need 3.3v and 5v power supply in your system? 12 / 12
sec asic DAC1353X 1.2v 8bit 2msps dac analog history card version date modified items comments ver 1.0 01.01.30 preliminary version all pictures and texts are modified with dac1326x datasheet. the format ant fonts of datasheet are same with dac1326x's datasheet. reference datasheet dac1236x dac1264x_ra dac1326x

▲Up To Search▲

Price & Availability of DAC1353X

	To Download DAC1353X Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .